(a) Field of the Invention
This invention relates to a method for planarizing the surface of an interlayer insulating film in a process for forming a multi-layered interconnection layer of a semiconductor device.
(b) Description of the Prior Art
In order to prevent a possible breakage of interconnection layers, or a possible short-circuiting between the interconnection layers, in a high-integration semiconductor device of a multi-layered interconnection structure it is necessary to form the surface of the interlayer insulating film as flat as possible. Various methods have been developed to planarize the surface of such an interlayer insulating film. Of these conventional methods, an etch-back method is known as a relatively simpler, useful method.
FIGS. 1(A) to 1(E) are cross-sectional views showing main steps of the known etch-back method. In this method, as shown in FIG. 1(A), an Si.sub.3 N.sub.4 film 2 is formed as an underlying insulating film on a thermal oxide film 1, by virtue of a lower-pressure CVD method, which overlies the silicon semiconductor substrate 10; a first interconnection layer 3 of an Al-Si alloy is formed on the Si.sub.3 N.sub.4 film 2; a plasma nitride silicon film 4 (hereinafter referred to as a P-SiN film) is deposited on the resultant structure by virtue of a plasma CVD method; and a positive type resist film 5 is formed on the resultant structure. When the respective film has a thickness of 1 .mu.m, then the P-SiN film 4 and resist film 5 are usually made to be 1 .mu.m and 2 .mu.m, respectively, in thickness.
Then, the resist film 5 and P-SiN film 4 are etched at the same etching rate, and that area "A" (See FIG. 1(A)) of the P-SiN film 4, which is located above the top surface and shoulds of the first interconnection layer 3, has its upper half area removed as shown in FIG. 1(B). In this case, a reactive ion etching (hereinafter referred as an RIE) is used as the etching method. The P-SiN film 4 is further etched by the RIE etching method and then stopped to leave a 0.3 .mu.m-thick area between the top surface of the first interconnection layer 3 and the surface of the P-SiN film 4 as shown in FIG. 1(C). At this time, a damaged area 4a is formed at the surface of the P-SiN film 4 due to the use of the RIE method and the area "A" of the P-SiN film 4 is completely removed.
The damaged area 4a provides a cause for leakage and, if removed by a chemical dry etching (hereinafter referred to a CDE) method, will be as shown in FIG. 1(D). Finally, an additional 1 .mu.-thick P-SiN film 6 is deposited by the plasma CVD method on the P-SiN film 4 as shown in FIG. 1(E), providing a flat interlayer insulating film.
However, the known etch-back method involves the following problems (1) to (4):
(1) The known etch-back method utilizes the CDE method when the damaged layer 4a--See FIG. 1(C)--resulting from the use of the RIE method is eliminated. Since in this case the P-SiN film portion in contact with the interconnection metal, i.e., that P-SiN film portion "B"--See FIG. 1(A)--situated near the side of the first interconnection layer 3 is liable to be etched due to, for example, a structural strain occurring at that portion, the P-SiN film portion "B" at the side of the first interconnection layer 3 is etched earler than the rest of the P-SiN film 4 at the time of etching the damaged layer 4a. As a result, the P-SiN film portion at the side of the first interconnection layer 3 is deeply etched, resulting in exposing the side surface of the first interconnection layer 3, for example, in FIG. 2(A) and, in the worst case, in causing an etching down to the Si.sub.3 N.sub.4 film 2, as shown in FIG. 2(B), underlying the P-SiN film 4.
(2) In order to prevent such an occurrence as shown in FIGS. 2(A) and 2(B), it is necessary that an about 0.3 .mu.m-thick P-SiN film portion be left, as shown in FIG. 1(C), between the top surface of the first interconnection layer 3 and the upper surface of the P-SiN film 4. However, the thickness of the P-SiN film 4 at the deposition time varies from lot to lot of the semiconductor substrate and a varying thickness is also observed in the respective lots. It is, therefore, impossible to detect a point of time at which an accurate etching is ended, failing to positively leave a 0.3 .mu.m-thick P-SiN film portion (a desired thickness), as shown in FIG. 1(C), between the upper surface of the first interconnection layer 3 and the upper surface of the P-SiN film 4. Conventionally, the etching requirements for a succeeding lot are set, taking the etching data of test pieces in a preceding lot into consideration. Thus, an operation error is liable to occur.
(3) In the RIE method, an overetching step cannot be carried out to eliminate a variation in etching depth from substrate to substrate, a variation in etching depth from lot to lot of the semiconductor substrates and a variation in etching depth of a single semiconductor substrate. Since the thickness of the P-SiN film area left between the upper surface of the first interconnection layer 3 and the upper surface of the P-SiN film varies, there is a variation in the through-hole etching time, the threshold voltage of a field area and the capacitance of a capacitor due to the presence of the interlayer insulating film and a consequent variation in the quality of semiconductor devices.
(4) In the steps as shown in FIGS. (A) and (B), the inorganic P-SiN film 4 and organic resist film 5 needs to be etched at the same etching rate. In this case, the operation and control of the RIE device needs to be performed under strict requirements when both the films differing in their etching property are etched at the same etching rate. Furthermore, a frequent checkup is required to see that the above-mentioned requirements are met. The RIE device is complex to manage and thus it is not easy to operate the RIE device.